CSC270   Homework #6

Microprocessor/Ram Interface

The circuit above shows a processor with an 11-bit address bus connected to two RAM circuits. Each one stores bytes of information, and the processor can read and write whole bytes at a time in each circuit.

The interface between the processor and the RAM contains two cascaded decoders. Review your notes and the textbook on cascading decoders to refresh your memory on how cascading works and why it is done.

The address bits A6 and A5 generated by the processor are not connected to anything.

When answering the questions below, please provide clear and detailed explanations.

1. How many distinct bytes of information can we store in the RAM circuit on the left?

2. How many distinct bytes of information can we store in the RAM circuit on the right?

3. What range of addresses generated by the processor activates the Y2 output of the top decoder?

4. What range of addresses generated by the processor activates the Y2 output of the second decoder?

5. What is the lowest address of the first byte in the leftmost RAM circuit? Rightmost RAM circuit?

6. What it the lowest address of the last byte in the leftmost RAM circuit? Rightmost RAM circuit?

7. How many different addresses map to a given byte in the leftmost RAM circuit? Rightmost RAM circuit?

8. What addresses map to the lowest byte in each of the RAM circuits.